META-DX2L lets routers, switches and line cards double their bandwidth by adopting the speeds of the 112G PAM4 interface
Routers, switches, and line cards require higher bandwidth, higher port density, and up to 5 Gigabit Ethernet (GbE) connectivity to handle the increased traffic in data centers caused by 112G, cloud services, and the applications of artificial intelligence (AI) and machine learning. To deliver this increased bandwidth, these designs must overcome the signal integrity challenges of the industry's transition to 4G (gigabits per second) of PAM1.6 SerDes (Serializer/Deserializer) connectivity demanded by optical connections, backplanes of the system and processors of packages of new generation. These challenges can now be overcome with the most compact 6200T (terabits per second) and low power PHY on the market from Microchip Technology Inc. (Nasdaq: MCHP), the PM2 META-DX56L, which reduces power per port by thirty-five percent if matched with its 4G PAM1 forerunner, called META-DXXNUMX, the first layer of physical pressure of the market in the order of terabits.
“The industry is embracing a 112G PAM4 ecosystem for high-density switching, bulk processing and optical connections,” said Bob Wheeler, chief network analyst at The Linley Group. "Microchip's META-DX2L solution is optimized to meet these requirements by connecting line cards to switching elements and optical equipment at multiple speeds for XNUMXGbE, XNUMXGbE and XNUMXGbE connectivity."
With its 1.6T bandwidth, high density and small size, 112G PAM4 SerDes technology, and its ability to achieve Ethernet speeds from 1 to 2GbE, the META-DX2L Ethernet PHY is a device with an industrial temperature range. offering multi-purpose connectivity to reuse the design edge in applications ranging from a retimer, multiplexer/demultiplexer, or demultiplexer/inverse multiplexer to a 1:4 mux. The interconnect and multiplexing/demultiplexing features are highly configurable, taking full advantage of the I/O bandwidth of the switching device to manage the flexible connections required on cards capable of running at multiple speeds and Compatible with a huge variety of optical connections. The PHY's low-power PAM5 SerDes lets you deliver next-generation interface speed for cloud data centers, AI and machine learning computing clusters, XNUMXG, and also infrastructure to telecom service providers, whether it's long-distance direct attach copper (DAC) cables as backplanes, or connections to optical devices.
“For the 56G generation we have introduced the first terabit PHY on the market, META-DX1, which has been followed by an equally transformative 112G solution that offers the capabilities that system developers need to solve the new challenges imposed by data centers in the cloud, 5G networks, AI and machine learning,” said Babak Samimi, vice president of Microchip's communications business unit. “With its ability to achieve up to 1.6T bandwidth in a low-power architecture with the smallest possible footprint, the META-DX2L PHY doubles the bandwidth of previous solutions on the market and sets a new level of efficiency. ”.
The META-DX2L comes in the smallest XNUMX x XNUMXmm package on the market, saving the space needed to achieve the line card densities required by hyperscalers and system builders. Here are some key features of the product:
• GbE PHY with 2x 4 GbE, 16x 100 GbE and 50x 25/10/1/XNUMX/XNUMX
• Supports Ethernet, OTN, and Fiber Channel data rates
• Supports proprietary data rates for AI and machine learning
• Integrated 2:1 multiplexer allowing high availability/high availability architectures.
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• Highly configurable interconnection for multi-speed services on any port
• Non-stop latency leaving IEEE XNUMX Class C/D PTP at any level of the system
• FEC termination, monitoring and conversion between multiple interface rates
• 112G PAM4 SerDes of thirty-two LR (long-reach) programmable to optimize consumption with respect to performance
• Compatible with DAC cables, including autonegotiation and link training
• Industrial temperature range for outdoor applications
• Comprehensive Software Development Kit (SDK) with easy upgrade, hot boot capabilities and support for the proven META-DX1 SDK
Microchip provides a full range of proprietary design products, reference designs, and evaluation boards for customers to build systems based on META-DX2L devices. In addition to its Ethernet PHY technology, Microchip also provides a total system solution to system vendors consisting of PolarFire® FPGAs, the ZL30632 high-performance PLL, oscillators, voltage regulators, and other components previously ratified as a system with META-DX2L for expedite the production of designs.
Product availability
Samples of the first META-DX2L devices are expected in the fourth quarter of 6200. For more information, visit the PM2 META-DXXNUMXL website or contact a Microchip sales representative.
