Figure 1. COM-HPC Mini is the most important addition to version 1.2, elevating the performance of high-end embedded clients to mobile and fixed devices with extreme space constraints.
The publication Markt & Technik speaks with Christian Eder, President of the COM-HPC working group and Director of Market Intelligence at congatec, about the main innovations of this still young standard for high-performance COM modules.
Mr. Eder, the COM-HPC specification has been around for two and a half years. How has demand evolved over this time?
COM-HPC is designed for high-performance COM (Computer-on-Modules) modules that can be used as modular servers and as modular clients. There is a high demand for such modules due to increasing digitalization and IIoT requirements, use of artificial intelligence, vision-based situational awareness, and spiral data processing needs. Developers working on new designs in these application fields have no doubt that COM-HPC modules are the right solution. Nearly one in two new projects across the full range of PICMG standards, including COM Express and COM-HPC, uses COM-HPC, and the first OEM solutions with 12th Intel Core processors are already in mass production. and 13th generation and Intel Xeon D. So, the launch of COM-HPC was extremely smooth and acceptance was high from the beginning. The situation was very different when the COM Express specification was released. At that time we had to convince a lot more. There is undoubtedly a great advantage in involving manufacturers-independent bodies, such as the PICMG, in the specification of new form factors.
What can customers expect from the new revision?
There are some minor improvements to the specifications that make the standard even more universally applicable and improve the robustness of the designs. However, the most important innovation is the incorporation of a new ultra-compact modular footprint: COM-HPC Mini. This new specification offers high-performance features in an especially small format of just 95 mm x 70 mm. Even devices with limited space can now benefit from the spacious 400-pin interface and higher bandwidth offering. This includes Thunderbolt and PCIe Gen 5, as well as Gen 6 in the future, once the corresponding processors are available.
COM-HPC thus establishes itself as the most scalable standard for COM modules that covers a wide range of applications, from small form factor designs to edge servers. This simplifies the design process and facilitates the development of complete product families. Since COM-HPC modules not only support specific processors such as x86 or Arm, but also FPGAs, ASICs and AI accelerators, they provide a complete standard for the development of innovative applications based on the latest embedded systems and edge computing technologies.
Why is the Mini spec so important?
On the one hand, embedded devices always have limited space, and even the smallest ones need enormous bandwidth for Intelligence.
Artificial and situational awareness. On the other hand, the 95mm x 70mm footprint is perfect for migration from COM Express to COM-HPC. In terms of space requirements, COM-HPC Mini modules fit into any design developed on the basis of COM Express Basic (95 mm x 120 mm) or Compact (95 mm x 95 mm). This makes migration much easier, so we expect a lot from this form factor in the long term.
But, COM-HPC Mini has 10% fewer pins than COM Express Type 6. Doesn't that limit the capabilities?
No. COM-HPC Mini is aimed at small, mobile devices, not at stationary systems, often very complex, with countless interfaces. The developers who have taken full advantage of COM Express Type 6 are mainly users of COM Express Basic. They are migrating to COM-HPC Size A. After all, they do not want to lose the option of offering a significantly larger number of interfaces. At 95mm x 120mm, this form factor is also slightly smaller than the 95mm x 125mm COM Express Basic and offers extremely high interface variety and density. Just the fact that it incorporates 800 pins instead of 440 provides more interfaces and bandwidth. What's more, fast interfaces like PCI Express or Ethernet are even faster in COM-HPC.
Theoretically, the possible interface performance increase from COM Express Type 7 (Rev. 3.0) to COM-HPC Server is around a factor of 15. From COM Express (Rev. 3.0) to COM HPC Client, the performance of E /S can even be multiplied by 17.
Aside from the form factor and 400-pin connector, are there any other differences between COM HPC Mini and the other COM-HPC form factors?
Yes, the pin assignment is different. In some cases, it includes multiple options to allow the implementation of as many configurations as possible with the 400 pins to offer maximum flexibility in the smallest footprint. The voltage allocation of sideband signals has also been adapted to reduce power requirements and, even more importantly, to support low-power processors, which increasingly operate at 1,8 volts. This simplifies both module and backplane design, as fewer level converters are needed compared to maintaining the same specification for larger COM-HPC form factors. Therefore, it is not possible to install COM-HPC Mini modules on a motherboard designed for Size A because the two form factors are incompatible, both electrically and in terms of interface assignment. The heatsink is also flatter to allow for thinner designs. Additionally, MIPI-CSI support is not provided via the 400-pin connector, but rather via two additional 22-pin flat connectors.
So, in effect, the COM-HPC Mini specification has 444 pins. This design approach with additional connectors was adopted by analogy with SMARC and COM Express, where it has already proven itself. Compared to other mini form factors, there is also another figure that highlights why COM-HPC Mini represents the absolute high-end: in addition to the higher pin count, support for up to 107 watts leaves significantly larger power reserves than 15 watts which are usually possible with SMARC.
Figure 2. COM-HPC 1.2 specifies a new connector for all COM-HPC sizes. Its plug increases the stability of the connection between board and connector.
Could you explain multiplexing a little to us? Doesn't it lead to arbitrary configurations, which can lead to incompatibilities?
Compared to the COM-HPC Client, with its higher pin count, the Mini specification offers 8 high-speed data channels for fast USB 3.x/USB 4 data lines and for digital display interfaces (DDI). However, not all data channels can be used for every purpose. Therefore, we have predefined five flexible options to scale the 8 SuperSpeed lanes between DDI and USB assignments. In addition to 2x DDI and 4x USB3 on one side and 4x USB4 on the other, variants with 1x DDI, 1x USB4 and 4x USB3, as well as 1xDDI, 2x USB4 and 2 USB3, and 3x USB4 and 2x USB2 are also possible. However, these are the only assignments allowed, providing planning certainty. The same goes for the allocation of PCIe, Ethernet and SATA.
Arm developers have long been aware of the SERDES principle introduced with COM-HPC, which has proven effective. However, to understand the potential of each individual module, it is necessary to consider the significantly larger number of combinations. To some extent, SATA is also a concession to current legacy designs. However, this option is rarely used as the numerous PCIe interfaces also enable fast NVME flash mass storage.
Figure 3. The new Mini form factor completes the COM-HPC specification, making it the most scalable COM standard on the market.
Let's take a look at the COM-HPC server portfolio. What is appearing here?
When the Intel Xeon D processors, codenamed Ice Lake D, were released, it was interesting to note that OEMs don't seem to need all of the memory bandwidth of these processors. This means they can rely on the Size D, which offers only 4 instead of 8 RAM slots. The reason for this phenomenon is that mixed critical edge server applications do not have to handle RAM-intensive server workloads. Rather, they must host multiple real-time applications in parallel and therefore need as many cores as possible. They must also meet the requirements of industrial communication with many small message packets that need to be processed in real time. Also in this case, memory space is not as crucial as in web servers with databases used by thousands of people simultaneously.
Let's now move on to the new features that apply to all form factors in the specification. What are the most significant changes?
There are two points to mention: Firstly, the connector has been optimized to further increase robustness. Second, COM-HPC is now fully PCIe Gen 6 qualified.
Figure 4. COM-HPC Mini has several multiplexed pin assignments, such as SERDES for PCIe, GbE and SATA. The 8 SuperSpeed channels can also have different DVI and USB interfaces.
Does the new connector also affect the motherboard?
Yes, two small holes are required to increase sturdiness. And the metal reinforcements on the sides of the connector are welded to increase mechanical stability. Other than that, nothing changes. The new reinforced connector can only be used if the second hole is also present. However, both the old and new connector can be used with the same SMT soldering process. In this sense, only a small change in the motherboard design is necessary to comply with Rev. 1.2. While I anticipate the old connector will still be available, it makes sense to avoid it for newer motherboard designs. The changeover poses no problems: the old and new connectors can be used in all combinations. It should be noted that the new connector will be available from at least three manufacturers. In addition to Samtec, Amphenol and All Best, this new variant can now also be manufactured under license, allowing for second-sourcing strategies.
What changes have had to be made to PCIe Gen 6 designs? Are there already processors compatible with this bandwidth and who needs this performance?
In general, it is already possible to design motherboards for Gen 6 even though there are no Gen 6 compatible processors yet. However, they will be available in the not-too-distant future. To integrate them, the motherboard must be prepared for PAM4 modulation instead of PAM2. In addition to the values 0 and 1, this uses two intermediate stages, with 2 instead of 1 bit per transmission. As this upgrade does not change the transmitted frequencies, few new challenges to signal integrity are anticipated. However, careful design is still important, as Gen 6 requires even greater attention to signal noise than Gen 5. The higher bandwidth of 8 GB/s per channel is necessary, for example, for graphics. This enables up to 128 GB/s across 16 channels, making it possible to transmit increasingly higher resolution frames at faster rates and with greater color depth. 100 GbE is already standard in many areas and this bandwidth must also be transmitted to the processor. USB is also getting faster.
Are robust embedded designs possible with these performance increases?
Fortunately, we have positive advances in manufacturing processes towards 7nm and smaller, as well as in 3D technology. This allows performance to be doubled with the same TDP. We will soon launch new processors with exactly this capability. Therefore, we can further increase performance by staying within the performance limits with passive cooling. This is also the only way to develop embedded systems that meet increasingly demanding sustainability requirements, including climate neutrality.
Thank you very much, Mr. Eder, for this interview.
Figure 5. When deploying COM-HPC server modules, embedded OEMs still tend to use Size D with 4 RAM slots. This is because many small data packets typically need to be processed in real time at the edge. However, there are 8-socket solutions for larger memory needs.
