FPGAs – Available debugging and analysis methods
Technical article provided by AFC Ingenieros SA and based on information from Tektronix
Juan Ojeda (jojeda@afc-ingenieros.com)
The growth in size and complexity of designs continues to make the verification process the most critical bottleneck in FPGA-based systems. Limited access to internal signals, advanced FPGA packages, and electrical noise on the printed circuit board all contribute to making debugging and design verification the most difficult process in the design cycle—to the point that the majority of the design cycle time can easily be spent debugging and verifying the operation of the FPGA. To aid the design verification and debugging process, new tools are required to make it easier to debug the design while keeping the FPGA running at full speed. This technical article focuses on tips and techniques that can help make debugging FPGA-based systems more effective. 
