Demand for NAND-based digital memory is booming, driven by increased use of devices spanning consumer and mobile markets, automotive and industrial sectors, and the emerging Internet of Things (IoT).
Since Toshiba introduced NAND in 1984, the technology and market landscape has evolved significantly. NAND bit densities have increased more than 2000 times due to the size of the process node going from 700nm to 15nm, and the introduction of new technologies at the cell level.
Accompanying this increase in density has been a dramatic reduction in the price per Gb, which has fallen even faster than bit density has increased – making NAND the storage medium of choice for many applications.
However, although the price per bit has decreased, moving to the latest technologies and processing nodes is not so easy. One of the main challenges for those who want to use the latest pure NAND designs in their devices is that newer NAND technologies tend to require more powerful error correcting code (ECC) engines in controllers – and this has become a “endless race”, in general, as there is often a waiting period for controllers to catch up.
For example, only 1 ECC bit per 512bytes is required for single level cells (SLC) NAND up to 43nm. This increases to 8bits ECC per 512bytes for 24nm SLC NAND, making the switch from 43nm pure SLC NAND to 24nm pure SLC NAND causing a significant negative performance impact unless more advanced controller technology is implemented.
Wear Leveling
Although the technology exists to make NAND on even smaller process nodes, the decrease in endurance and reliability of the cells comes into play. And furthermore, NAND cells that can store multiple bits have been developed – single level NAND cell (SLC) can store 1 bit per cell, multilevel NAND cell (MLC) can store 2 bits per cell, while Triple-level NAND cells (TLC) can store 3 bits per cell. However, write/erase endurance suffers from such approaches – SLC can support around 60.000 cycles, MLC 3000 cycles, and TLC 500 cycles (assuming the same ECC algorithm).
Because NAND memory blocks can be degraded and damaged, an upper limit is assigned to the number of writes to each NAND memory location. "Wear leveling" algorithms also need to be built into the NAND controllers to ensure that NAND memory locations are used evenly.
In calculating system lifetime using NAND reliability, it is important to remember that memory management functions cause more writes to each cell than the number of data bits that are initially written.
This is because memory management functions can involve moving data from one place to another, resulting in multiple cell writes for each bit of data to be stored.
While NAND writing/programming takes place on a page-by-page basis, the erase functions remove entire blocks (consisting of multiple pages).
When a block is prepared for deletion, the data to be kept is first copied to other blocks. This page crawl before the block is cleared is called garbage collection.
Reducing the load on the controller
For many existing applications that use SLC NAND memory, such as industrial designs, communications processors, and automotive systems, 1-bit ECC is implemented in host software without any significant effect on application performance.
Migrating to “state of the art” memories that require 4, 8, or even 24-bit ECC significantly increases the demand on the processor, reducing performance. In order to avoid this performance penalty, NAND chips with integrated ECC have become the preferred solution.
Toshiba's BENANDTM (with integrated NAND ECC) offers such a solution and removes the burden of ECC from the main processor without the need for an additional hardware controller.
BENAND uses the well-established, common NAND interface, ensuring compatibility with pure SLC NAND Flash in areas such as command sets, device operation, packaging, and pinout. The core system handles issues such as bad block management, wear leveling, address assignment, and garbage collection in the same way as with pure SLC NAND.
BENAND devices are available from 1 Gb to 8 Gb in density, packaged as standard TSOP-I-48-P and 63-ball BGA devices that are pin-compatible with popular SLC packages.
A small 67 ball 6,5mm x 8,0mm BGA version is also available, allowing designers to meet tight space constraints in new designs. Direct pin and package compatibility between pure SLC NAND and BENAND allows their drop-in replacement when upgrading to next-generation FLASH.
This approach has enabled Toshiba engineers to help customers integrate BENAND into both existing and new designs, offering the benefits of migrating to the latest technology while avoiding the high costs associated with significant redesign of the system or long-term use of legacy technology.
Eliminating the need for a NAND controller
Embedded controllers perform operations such as error correction, wear leveling, and bad block management to ensure that the NAND memory functions properly.
e.MMC solutions are typically based on MLC NAND and combine pure MLC NAND with a NAND controller. To increase memory reliability when data is changed at high frequency, managed MLC can use a mode called pSLC (pseudo-Single Level Cell), which emulates SLC NAND by storing only one bit in each MLC cell. This approach allows data to change ten times more frequently than with standard MLC NAND operation, with comparable levels of reliability. This can be useful in applications such as set-top boxes, which can pause live TV, where data is frequently overwritten.
The pSLC mode needs to be activated during the first boot and the NAND controller manages the MLC memory as normal.
The latest version of the JEDEC standard, e.MMC v5.0, defines a higher speed interface (HS400) to meet the needs of high performance systems. It also includes an update procedure that allows the installation of a new version of the e.MMC device driver firmware, once the product is in the field. A SLEEP mode notification feature allows for a safer transition to lower power sleep modes.
A key feature of any version is compatibility with e.MMC products that are compliant with earlier versions of the standard. For that reason, while it is possible to get better performance from the new v5.0 pin layouts, the new layout is also backward compatible.
Future trends
As with all digital ICs, there is a trend toward higher performance and lower power consumption in denser packages; and Toshiba uses its 15nm process node in its e.MMC flash to meet these needs. There is also a need to ensure that the life of older products can be extended, and BENAND is responding to those needs by allowing engineers to specify the latest NAND technologies without having to upgrade controller hardware.
There is also a trend of expanding the operating temperature ranges for e.MMC NAND flash products. The standard operating temperature range of e.MMC for consumer electronics is -25 to +85°C. Toshiba has started manufacturing devices that are suitable for automotive and industrial infotainment applications, with a range of operating temperature between -40 and + 85 °C.
Looking a little further into the future, super high-end smartphones and tablets will be the first to move from the current e.MMC format. The technology has evolved into a new format called Universal Flash Storage (UFS), which is currently in the early stages of volume production. With initial data throughput of 300 MB/s (2,9Gbps per line) the devices are aimed at the high end of the consumer electronics sector. The next generation specifications achieve line speeds of 5,8 / 11,6 Gbps and can be deployed as multi-line solutions. Data can be transferred through the serial bus in both directions, up and down simultaneously (figure 4).
Smart device designers demand faster, smarter, higher capacity NAND devices that enable backwards compatibility and easier application. With extensive experience developing its own technologies, both NAND and controllers, Toshiba designs both together to deliver performance-optimized and reliable memory solutions for current, future, and even past devices.
