Author: Sudarshan Deo, Director of Software R&D, Siemens Digital Industries Software
The increasing complexity of artificial intelligence (AI) workloads, particularly those using transformer-based models, is exceeding the capabilities of traditional transistor scaling. This has led to a fundamental shift in chip design philosophy: instead of adapting software to existing hardware, silicon is now being designed specifically for AI workloads. This "AI-centric chip design" paradigm demands hardware capable of handling massive parallelism and high-speed data movement within strict thermal and power constraints.
3D integrated circuit technology directly addresses these demands by vertically integrating multiple chips, such as high-bandwidth memory (HBM) and logic, using through-silicon vias (TSVs). This vertical integration dramatically increases bandwidth (for example, HBM3 and HBM3E stacks provide more than 1 TB/s per stack, up from 800 GB/s) and reduces latency, making it an indispensable technology for advanced AI accelerators and high-performance computing.
However, this advancement brings significant design challenges, such as:
- Energy and thermal management: Artificial intelligence chips consume a lot of power. The stacking density of 3D integrated circuits increases heat dissipation problems, requiring sophisticated cooling solutions and precise thermal and power analysis to prevent thermal runaway and performance degradation.
- Wall of memory: AI workloads often suffer from bottlenecks due to data movement between the processor and memory. HBM integration involves complex 3D stacking and nanoscale junctions, where even minor interconnection failures can compromise the integrity of the entire chip.
- Architectural complexity: Modern AI chips can contain billions of transistors. The design of these highly complex 3D integrated circuits requires meticulous planning. multichipletConnectivity between chips and system-level modeling surpasses the capabilities that traditional EDA tools can manage through manual methods.
- Scalability and modular design: the transition to architectures based on chiplets And the stacking of 2.5D/3D integrated circuits, while allowing for modularity and scalability, also complicates hypothetical scenarios «what if» related to signal synchronization and vertical power supply.
These challenges underscore the need for advanced solutions that go beyond traditional EDA workflows, making AI-driven EDA not just beneficial, but essential. To address these challenges, AI is transforming EDA by embedding machine learning (ML) and reinforcement learning (RL) techniques directly into design tools. This enables the automation and optimization of the entire design flow, tackling the immense complexity that human engineers can no longer manage alone. Let's look at some key trends where 3D integrated circuits intersect with AI.
Intelligent Design Space Exploration (DSE)
3D integrated circuit architectures are exponentially complex, forcing designers to balance thousands or millions of interdependent variables (chip partitioning, material stacks, plant layout, interconnect topology, and power supply) while optimizing power, performance, and area (PPA), reliability, and cost. Manual iteration is slow and prone to suboptimal results.
AI, through machine learning (ML), reinforcement learning (RL), and surrogate modeling, exponentially accelerates design success analysis (DSE). It allows teams to predict outcomes more quickly. AI models can rapidly assess the impact of design decisions.
AI can learn from previous iterations. The knowledge gained from past designs can be applied to new projects, reducing the time it takes to implement next-generation architectures.
It can be used to discover unconventional architectures. AI can identify optimal architectural plans that traditional methods might overlook, delivering quantifiable improvements under multiple constraints.
AI is especially useful when it can complement and enhance human expertise. AI-powered copilots and agentic systems allow a single design engineer to manage multiple complex blocks simultaneously, significantly increasing productivity.
Figure 1. DSE loop driven by agentic AI/LLM and assisted by predictive or surrogate models applied to the electrical, thermal and mechanical stress workflows of 3D integrated circuits. (Source: Siemens Digital Industries Software)
AI-driven DSE can be implemented in real 3D integrated circuit programs by combining an AI/LLM layer with predictive or surrogate model-assisted optimization and closing the loop through implementation plus three final validation flows for electrical, thermal, and mechanical stress analysis.
Figure 1 shows a closed-loop DSE workflow in which an autonomous AI/LLM layer interprets optimization questions and KPI constraints and then orchestrates implementation and integration. The workflow connects to three final multiphysics validation flows: electrical analysis, which generates artifacts such as S-parameters and eye diagrams; thermal analysis, which generates temperature maps and hotspot information; and mechanical stress analysis, which generates reliability-relevant results. Feedback on implementation and KPI scoring drives iterative refinement toward an optimal solution.
In Figure 1, agentic AI can be positioned “on top” of the implementation and multiphysics engines to make DSE viable at the 3D integrated circuit scale. The AI layer structures the optimization problem into KPIs and explicit electrical constraints (pass/fail checks, weighted scoring, constraint indicators), selects experiments, triggers tool runs, and uses surrogate/predictive models to reduce the number of costly high-fidelity iterations. Importantly, the same DSE loop can encompass three coupled workflows—electrical, thermal, and mechanical stress—so that improvements in one area do not inadvertently cause failures in another.
At the 3D integrated circuit scale, the limiting factor is usually not the concept of optimization, but rather the ability to safely orchestrate many heterogeneous tools, executions, and artifacts across different computing environments. This is where an MCP-based tool infrastructure comes in.
Figure 2. Reference architecture of an MCP tool infrastructure for 3D integrated circuit agent design workflows (Source: Siemens Digital Industries Software)
Figure 2 illustrates a “tool infrastructure” based on an MCP (Model Context Protocol) server that sits between an agent optimizer and the heterogeneous set of executables used in 3D integrated circuit programs. Instead of point-to-point integrations, each capability is exposed as an MCP server with well-defined and logged inputs/outputs for discovery. An MCP host/bridge mediates the secure execution of tools, environment configuration, data movement, and routing to local machines or high-performance computing (HPC) schedulers, while capturing logs, versions, parameters, and artifacts produced. This architecture enables scalable experimentation with multiple tools and closed-loop optimization by normalizing results in KPI/evidence repositories and making each execution traceable and repeatable across teams, sites, and toolchains.
Automated scaling dependent on power and temperature
In 3D integrated circuits, power and temperature are closely related, creating a nonlinear feedback loop: temperature modifies leakage and power, which in turn modifies temperature. To converge quickly and accurately, teams need a scalable way to generate temperature-dependent power inputs for thermal analysis without having to repeatedly rerun the entire characterization under each extreme condition.corner).
Figure 3. AI-driven temperature-dependent power modeling for design space exploration. (Source: Siemens Digital Industries Software)
The temperature-dependent scaling flow (Figure 3) allows capturing the reference power in a simple cornerCreate temperature-scaled libraries, map temperature-based leaks at the cell level, normalize and generate multi-temperature power inputs, and close the loop with a 3D thermal analysis.
AI-ready chip design data
The effectiveness of AI models depends on the quality and accessibility of their training data. 3D integrated circuit design generates petabytes of heterogeneous data (design, electrical, thermal, mechanical, manufacturing, design exploration results, simulation results, characterization data, PDK information) that often reside on disparate and isolated systems with inconsistent formats or noise.
Preparing this massive, multi-domain data for AI requires a strategic investment in design and IP data management. Selecting, labeling, and ensuring the quality and accessibility of data throughout the entire design lifecycle is crucial. Scalable storage and compute platforms are also necessary, as high-fidelity simulation results demand a robust infrastructure.
Without these foundations, AI models risk learning spurious correlations, amplifying biases, or producing unreliable results. This underscores the importance of a holistic approach to data management within the EDA ecosystem.
Addressing the challenges of 3D integrated circuits with industrial-grade AI
Industrial-grade AI is based on five fundamental principles:
- Precision: to ensure that all results are quantitatively correct and conform to strict physical laws and engineering constraints, where even a minute error can be critical.
- Verifiability: provide transparent and traceable decision-making pathways so that engineers can accurately audit how and why AI has arrived at a specific result.
- Sturdiness: Maintain high performance, reliability, and consistency even with new, noisy, or incomplete datasets.
- Generalization: to successfully apply the knowledge and models trained in one design problem to new and previously unseen engineering problems.
- Usability: Seamless integration with CAD/CAE software tools and established workflows without the need for extensive retraining.
This industrial-grade AI approach augments human expertise, alleviates the burden of manual workflow management, and improves engineering performance, ensuring that rigorous multiphysics validation can scale alongside increasingly demanding PPA requirements and time-to-market constraints.
Conclusion
As 3D integrated circuit systems become more complex and heterogeneous to meet the demands of the AI era, combining human expertise with AI-enhanced design methodologies will be essential. Legacy chip designs are no longer sufficient to handle the massive parallelism and high-speed data movement required by modern AI workloads within strict temperature and power constraints. Industrial-grade AI solutions enable design teams to overcome these challenges. By integrating intelligent design space exploration, automated thermal and energy co-analysis, and robust data management, AI is transforming the EDA ecosystem.
Read the extended technical report here: Three design imperatives to accelerate 3D IC design with AI
