Home Articles Power-on-Package supplies up to 1000A to AI process chips

Power-on-Package supplies up to 1000A to AI process chips

Recent advances in computing for artificial intelligence (AI) have significantly increased the need for high-power processing. Using high-end multi-core ICs with billions of transistors, AI process chips draw hundreds of amps and present a challenge for the power system designer. Engineers building high-density, high-power systems-on-chips now have a new tool that can help them simplify the power part of the project: Power-on-Package (PoP) packaging, which integrates the back-end and in the feed chain on the substrate of the process chip, as can be seen in Figure 1, and offers advantages in terms of performance and efficiency. (A “process chip” in this case describes either central processing units or CPUs, graphics processing units or GPUs, complex FPGAs, or system-level ASICs.)
The evolution of semiconductor technology has caused enormous changes in the power requirements of devices such as processor cores. Core voltages have dropped from 5V to 3,3V, then to 1,8V, and are now below 1V. The progressive reduction in size allows more logic circuits to be integrated on a chip, to such an extent that many complex devices have thermal limitations: the amount of heat that the package is capable of dissipating sets the limit of what can be integrated on the chip . Since thermal design power is often well in excess of 100W, the required input current has increased enormously due to the drop in supply voltage, and it is no longer rare to find values ​​of the order of several hundred amps for current. . In practice, process chips are often powered by multiphase regulation from a distributed 12V bus, but supplying hundreds of amps is very difficult with this technique.

As the supply voltages have decreased, the quality required of the supply has increased. Since the logic switching margins constitute a significant part of the very low voltage supply, the supply itself must be very stable and generate a very low level of noise in order to eliminate the possibility of voltage transients generating false trips. . At currents of hundreds of amps, even the slightest resistance in the power supply path can cause unacceptable voltage drop (I²R). The same is true for the power path as a whole, since it can generate undesirable losses. In addition, process chips are often used to switch entire processor cores or other large pieces of logic on the order of nanoseconds, requiring high current spikes that the power must be able to satisfy without generating unwanted transients. The PoP solution represents the convergence of distinct but related trends in power supply design: separation of voltage regulation and transformation functions, and gradual movement of the last stage of power systems to the point of load.
In its pursuit of more efficient and higher performance power systems, Vicor has developed even more advanced modules and evolved its Factorized Power Architecture (FPA) in a series of steps to the current PoP solution that enables the use of FPA. in high-performance supercomputing applications. Factored power allows distribution of a higher voltage, typically 48V, throughout a system and on the main board with a single stage conversion from heat to point of load. In conventional solutions available on the market it is difficult to achieve such a high conversion factor. Vicor has developed a topology called SAC (Sine Amplitude Converter) with which it is possible to obtain very high factors efficiently and with low levels of loss and noise. With SAC, the power MOSFETs only switch at the crossover points with zero voltage and current, thus almost completely eliminating switching losses. In addition the switching frequency can be high and this minimizes the need for output filtering capacity.

In the PoP solution, a module called a modular current multiplier (MCM) is placed directly on the substrate of the process chip. As its name suggests, the MCM works as a fixed-factor DC/DC converter (in practice it is a “DC transformer”). It generates the high voltage and high current required by the silicon from the lower current and higher voltage coming from the process chip's substrate/package pins, and is supplied through the substrate or printed circuit board. on which the process chip sits. This configuration offers several obvious advantages: the highest current spike is the path from the MCM to the process chip; a very low resistance generates low I²R losses; and a very low inductance in this path contributes to improve the response to transients of the MCM.
This refers to the “last inch”, that is, the final millimeters in the power path to the process chip, as Figure 2 shows. In a conventional solution, the copper tracks in the last inch, as well as the package pins, can have a resistance of the order of a few hundred micro-ohms. For a high-end process chip drawing 200A, a 500μΩ path would result in a 100mV drop, that is, more than 10% of the sub-1V power rail. Even more problematic is that the I²R losses in this example add another 20W of heat generated in the vicinity of the process chip. To overcome these obstacles, the PoP-based technique places the MCM on top of the device package, allowing all power to be supplied to the process chip via the main board in order to still achieve high voltage levels and low current levels. .

In this way, the losses in the printed circuit board itself are reduced and copper can be saved in the power planes. The only way to provide a sufficiently low impedance path without a converter on the substrate is to assign many pins to the power. However, if the MCM is placed directly on the process chip substrate, the power supplied from the PCB to the process chip package carries currents that are typically about 50 times smaller than the value needed to power the core. . This decreases the number of pins for power on the process chip substrate by up to 10 times. Similar to a traditional FPA-based design, the PoP system incorporates a pre-regulation stage before the current multiplier: an MCM Driver module (MCD) that mounts on the main board.
With the goal of offering a suitable physical format for mounting on the process chip substrate, Vicor has configured the SM-ChiP package (Figure 4) through a new development of the techniques used in its VI Chip modules. The SM-ChiP is based on surface mounting with minimum impedance terminations to the substrate (or main board). The MCM3208S- 59Z01A6C00 module measures 32 x 8mm and 2,7mm in height; a couple of them supply 2 x 160A continuously or a 2 x 320A peak current, for which it has the MCD3509S60E59D0C01, an MCD that measures 35 x 9 x 4,9mm that is placed on the printed circuit board and It is capable of reaching an average power of 400W and a maximum of 600W.

For even higher currents, two 4608 x 59 x 01mm MCM5S00Z46B8T2,7 modules, each for an average current of 300A and a maximum current of 500A, allow the system to reach a maximum current of 1kA. The attached 4609 x 60 x 59mm MCD MCD0S00E46H9T4,9 mounts on the main board to provide 650W average power and 1000W peak power. The high current required by the new generations of supercomputers requires rethinking the power supply. Now that a couple of centimeters of distance between the regulator and the process chip are key to power losses, PoP packaging offers a solution that allows obtaining the high levels of efficiency and power density that are essential for process chips. high power process. The PoP eliminates the barriers that characterize conventional power solutions thanks to a higher distributed voltage (48V) and voltage transformation in the final stage directly adjacent to the process chip, which in practice eliminates the last inch.