Kevin Tretter, Senior Product Marketing Engineer, Microchip Technology inc.
As their name indicates, the analog-to-digital converter (ADC) are special amplifiers specifically designed to work with ADCs, including architectures based on successive approximation, pipelines, and delta-sigma. These special amplifiers are critical circuit components that allow the ADC to work at its best, as will be discussed in the following sections.
What is an analog-to-digital converter driver and why do I need one?
As their name suggests, the analog-to-digital converter (ADC) are special amplifiers specifically designed to work with ADCs, including architectures based on successive approximation, pipelines, and delta-sigma. These special amplifiers are critical circuit components that allow the ADC to work at its best, as will be discussed in the following sections. The need for analog signal conditioning, including ADCs, continues to grow as sensors become more abundant in various end markets. These end markets include:
- Communications
- Medicine
- Consumer goods
- Industrial
- Automobile
In the case of ADCs, the market trend is towards higher resolution and speed devices as the cost of these solutions becomes more affordable.
Understanding ADC inputs
Before talking about the technical functions that an ADC controller requires, it is necessary to briefly review the input architecture of current ADCs. A differential signal can be defined as two nodes that have equal but opposite signals around a fixed point (the common mode level). The two signal nodes are often referred to as positive and negative (non-inverting and inverting), as shown in Figure 1.
In the example above, the full scale input voltage is 5V peak-to-peak differentially, with each leg swinging 2,5V peak-to-peak. The common mode level in this example is 2,5V. Most current high-performance ADCs implement a differential input architecture, as it provides superior performance (relative to single-ended inputs). These performance advantages include the ability to reject common mode noise and common interfering signals and a 6 dB (or a factor of 2) increase in dynamic range.
ADCs can present a particularly difficult challenge for system designers, as they offer a variety of different input sampling architectures that must be considered at the system level. For the purposes of this discussion, we will focus on ADCs that use a switched capacitor structure to perform input sampling. In its most basic form, this input structure is made up of a relatively small capacitor and an analog switch, as shown in Figure 2 below.
When the switch is set to position 1, the sampling capacitor charges up to the sampling node voltage, in this case VS. The switch is then moved to position 2, where the accumulated charge on the sample capacitor is transferred to the rest of the sample circuitry. The process starts over.
An unregulated switched capacitor input, such as the one described above, can cause major problems at the system level. The current needed to charge the sampling capacitor to the proper voltage must be supplied by the external circuit connected to the input of the ADC. When the capacitor is switched to the sampling node (switch position 1 in Figure 2), a large amount of current will be required to start charging the capacitor. The magnitude of this instantaneous current is a function of the size of the sampling capacitor, the frequency at which the capacitor is switched, and the voltage present at the sampling node. This switching current can be described by the following equation:
In the example above, C is the capacitance of the sampling capacitor, V is the voltage present at the sampling node (in this example denoted as VS), and f is the frequency at which the sampling switch is turned on and off. This switching current gives rise to high current spikes at the sampling node, as illustrated in Figure 2.
The implications of this switching current must be taken into account when designing the analog circuitry ahead of the A/D converter. As this current passes through any resistance, a voltage drop will occur, resulting in a voltage error at the sampling node of the A/D converter. Distortion can also occur if the input node is not fully seated before the next sample cycle.
Solution: ADC Drivers
Maintaining the sensor signal integrity required to take full advantage of these higher resolution and speed ADCs becomes a major challenge. As the resolution and speed of the ADC increase, the effects of noise and distortion on the sensor signal become more noticeable. At higher sample rates of ADCs, care must be taken to ensure that the input signal has settled before the sampling event and that higher bandwidth signals do not overlap in the bandwidth of the signal of interest. .
To overcome these signal conditioning challenges, many ADC applications require an ADC controller that provides sufficient settling and anti-aliasing. As described above, most modern ADCs implement a differential input architecture. One of the main functions of the ADC controller is to provide single-ended to differential conversion of the incoming signal.
Another function of the ADC controller is to buffer the input signal, thus isolating the rest of the circuitry from charge injection at the ADC input node. The ADC controller provides instantaneous loading to ensure that the sample node settles within track time, thus minimizing any settle-related distortion.
Most ADC driver amps also provide a hardware pin that allows the user to level the common mode voltage. This feature is ideal for ensuring that the resulting differential signal is centered within the input voltage range of the ADC, thus maximizing dynamic range.
Finally, like most amplifier components, ADC drivers can provide input signal amplification as well as active filtering. Note that most ADC drivers are specified with a relatively low gain, typically gains of only 1 or 2 V/V. By keeping the closed-loop gain of the amplifier low, the loop gain is maximized, resulting in the least distortion. For example, if an amplifier has an open-loop gain of 100 dB and is set for a closed-loop gain of 200, or 46 dB, this leaves only 54 dB of open-loop gain headroom to ensure linearity, or about one part in 500. Therefore, it is common to have a separate gain stage that sits close to the signal source.
To get the most out of your data converter, the ADC controller must optimize performance while adding negligible distortion, noise, and settling time errors to the source signal. differential controller MCP6D11 is specifically designed to maximize the performance of high speed ADCs such as the MCP33131, which is a 16-bit, 1MSPS ADC SAR. For an example of how these two devices work together to maximize performance, see the evaluation board MCP331x1 (ADM00873).
