Author: Rolf Horn – Applications Engineer, DigiKey Electronics
The frequency source is often the hidden bottleneck in high-speed data converter and 5G radio designs. As data transmission speeds increase and 5G moves into higher frequency bands, performance demands become much more difficult to meet. The list of requirements continues to grow, often in directions that conflict with performance goals.
Like the foundation of a building, if the frequency source shifts, everything built on top of it is compromised. The local voltage control oscillator (VCO) is that foundation, and any instability there propagates throughout the system, where no amount of careful design elsewhere can fix it.
At the heart of every frequency synthesizer is a phase-locked loop, or PLL. The PLL is the mechanism that locks the output frequency to a precise reference and keeps it there. It's what separates a stable, controllable frequency source from a drifting oscillator.
Modern applications such as radios, radars, phased array antennas, multiband test equipment, and wireless infrastructures constantly hop from one frequency to another to avoid interference, support multiple channels, or electronically steer beams. Every time a system changes frequency, its PLL must relock. Until that happens, the signal is unstable and essentially unusable. This relock time directly impacts the overall responsiveness of the product.
A data converter works by measuring an incoming signal at precise, regular intervals, often millions of times per second. The clock determines when each measurement is taken. Any timing uncertainty in that clock, known as jitter, means that measurements are taken at the wrong time, introducing errors that appear as noise in the output. The faster the signal, the worse the effect.
In 5G radios, the same problem manifests differently. The local oscillator precisely places the radio signal at the correct frequency. Phase noise in the clock source results in sampling jitter, which directly limits the converter's signal-to-noise ratio (SNR) and ultimately contributes to system-level metrics such as the error vector magnitude (EVM).
In both cases, the result is the same: uncertainty in the frequency source introduces errors that cannot be corrected downstream. A converter specified for exceptional dynamic performance can only achieve its target figures if the clock driving it is equally precise.
In practice, the synthesizer's phase noise determines how much timing uncertainty builds up in the clock signal—expressed as RMS jitter, a single figure representing the average magnitude of those timing errors—and thus how much of the converter's noise and distortion budget is consumed before the signal is even digitized.
Design Considerations
When designing high-speed data converters and 5G applications, it is important to consider the trade-offs that can affect performance:
- Phase noise determines the background noise, setting the ceiling for the dynamic range to achieve the best possible signal clarity, regardless of how good everything else is. In a 5G radio, it determines whether the modulation scheme is even decodable at the receiver.
- The frequency range determines flexibility. A synthesizer that covers the target band without external multiplication or division simplifies the design, reduces the number of components, and eliminates the noise and complexity introduced by those additional stages.
- Blocking time determines how quickly the system can change channels or respond to dynamic conditions, which is critical in frequency hopping and beam steering applications.
A PLL locks a frequency by continuously comparing its output to a reference and making corrections. This correction process is governed by a feedback loop and, like any feedback loop, takes time to settle, as the loop must detect the error, respond to it, and stabilize before the output is usable.
In traditional designs, the same loop bandwidth that determines PLL response speed also directly affects phase noise performance. Widening the loop to lock faster worsens phase noise. Narrowing the loop to improve phase noise negatively impacts lock time. This fundamental trade-off meant that designers had to choose what was most important for their application and live with the consequences of that choice.
The latest generation of integrated fractional-N synthesizers directly addresses these trade-offs. Whereas previous solutions forced designers to choose between phase noise performance and integration level, the latest devices combine ultra-low phase noise with wide frequency coverage, fast lock-up times, and a compact size, consolidating into a single solution what previously required multiple discrete components.
For data converter synchronization, this means that background noise from the frequency source is no longer the limiting factor in the system's dynamic range. For 5G radio designs, it means that achieving the demanding error vector magnitude targets becomes a frequency source problem that has already been solved, rather than an engineering problem.
Modern radio frequency systems typically generate sampling clocks and local oscillators using fractional-N PLL synthesizers. While these architectures allow for extremely fine frequency resolution, modulating the divider ratio introduces quantization noise and fractional spurs that contribute to the overall phase noise profile. Noise from an amplifier or filter affects the signal, but noise from the frequency source corrupts the reference, and a poor reference undermines all blocks that rely on it.
The on-chip VCO simplifies the board design
Broadband frequency synthesis has traditionally meant assembling a signal chain from discrete components: external VCO, PLL, buffers, and the design headaches that entails. Analog Devices, Inc. (ADI) simplifies board design with solutions that integrate the VCO on the chip, collapsing that chain into a single device with fast calibration for frequency hopping, without sacrificing the phase noise and jitter performance needed by 5G radio designs and high-speed data converters.
The frequency change is not instantaneous. When a PLL receives the command to switch to a new frequency, it goes through three distinct stages before the output is usable. Initially, it receives the command to change. Next, it internally searches for the appropriate settings to generate the desired frequency; this search phase is the slowest part, typically taking between 100 and 250 microseconds in a modern broadband device. Finally, it stabilizes, ensuring that the output is clean enough for use.
The ADF4382 ADI directly addresses the slow intermediate step. Instead of performing a new lookup each time a frequency change is requested, it uses an on-chip lookup table with 32 pre-calculated settings at known points across its entire frequency range for rapid calibration. When a new frequency is requested, it finds the two closest stored points and interpolates between them to arrive at the correct settings almost instantly. This reduces the total lock-up time to less than 10 microseconds and as low as 2 microseconds.
Three devices feature a dual-core VCO with 512 overlapping bands. They also share the same figure of merit (-239 dBc/Hz), the same ultra-low jitter performance, and the same fast calibration capability. What differentiates them is their frequency coverage:
- The ADF4382 (Figure 1) covers from 687.5 MHz to 22 GHz at the output, making it the longest-range member of the family and the natural starting point for 5G millimeter-wave radio designs and other applications such as broadband radars and test instruments that need to operate at the upper end of the frequency range.
- El ADF4382A (Figure 2) is recommended for synchronizing high-performance data converters, covering output frequencies from 2.87 GHz to 21 GHz, with automatic alignment of the output to the input reference edge across multiple outputs. This enables designs using multiple converters synchronized from the same source with consistent timing relationships.
Figure 2. The ADF4382A is optimized for demanding clock applications in high-speed data converter systems. (Image source: Analog Devices, Inc.)
- El ADF4383 (Figure 3) extends the coverage downwards compared to the ADF4382, broadening its applicability to designs operating in lower frequency bands, while retaining the family's overall performance architecture, including fast calibration and the same figure of merit. It shifts the VCO range slightly downwards, from 10 GHz to 20 GHz, enabling output frequencies up to 625 MHz with internal dividers. It offers improved phase noise performance, making it well-suited for systems requiring exceptionally clean microwave clocks and local oscillators.
Figure 3. The ADF4383 extends coverage to lower microwave bands while offering even cleaner clock generation for high-performance RF applications and data converters. (Image source: Analog Devices, Inc.)
All three variants utilize an output divider architecture. The ADF4382 and ADF4383 dividers support division ratios of 1, 2, 4, 8, and 16. The ADF4382A incorporates divide-by-2 and divide-by-4 output dividers that generate frequencies in two specific subranges, respectively from 5.75 GHz to 10.5 GHz and from 2.875 GHz to 5.25 GHz.
This architecture allows designers to translate the high fundamental frequency of each component's VCO to a local clock or oscillator frequency suitable for specific design requirements. Because the output divider is located within the PLL feedback loop, the output can be automatically aligned with the input reference edge, greatly simplifying multi-chip synchronization.
Troubleshooting hardware problems with software
The programmable reference-to-output delay of the ADF4382 family, with sub-picosecond resolution, means that timing relationships between devices can be dialed in via software instead of relying entirely on the precise board layout. Thus, a historically difficult hardware problem becomes a manageable, programmable one.
When using quick calibration, the lookup table must be regenerated if the operating temperature deviates by more than ±20 °C from the temperature at which it was created. For designs that combine wide temperature operation with rapid frequency changes, such as automotive or outdoor industrial applications, this becomes a simple firmware consideration rather than a fundamental limitation.
For a product designer, the selection process is straightforward. Identify the target output frequency, check which range of variants cleanly covers it without requiring external multiplication or division, and select accordingly. In most cases, the device's internal output dividers will handle the translation from the VCO's fundamental frequency to whatever local clock or oscillator frequency the specific design requires. Whichever variant suits the application, the underlying performance architecture remains the same: the same figure of merit, the same fast calibration capability, and the same integration advantages.
Conclusion
By reducing frequency switching time, ADI's ADF4382, ADF4382A, and ADF4383 fractional-N PLLs aim to make frequency-hopping designs faster, more responsive, and more efficient without introducing timing risks. If requirements change, designs can be seamlessly migrated from one variant to another thanks to their shared architecture.
